For 8-bit memory devices error correction mechanisms

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Described herein are 8-bit wide data error detection and correction mechanisms that require fewer memory chips and therefore provide reduces system complexity and reduced system power consumption as compared to traditional mechanisms. This technique relies on testing a fixed set of possible solutions in order to correct the fault. This error code provides a very high error detection rate, but requires a set of error trials to correct the detected faults. The extra correction latency for infrequent errors may be acceptable given a low frequency. For repeated corrections, a log may be maintained to simplify error correction.