| 简介 |
The present invention relates to an apparatus and a method for reducing the power consumption of a synchronous integrated circuit that utilizes the sparse activity of an artificial neural network. The present invention detects the activity of a neuron in the artificial neural network and blocks the clock of a processing element for sparse activity, thereby reducing unnecessary dynamic power consumption.(AA) Start(BB) End(S120) Turn on a clock(S130) Output an operation performance result value(S150) Turn off the clock(S160) Output a basic valueCOPYRIGHT KIPO 2017 |
客服热线：
手机版
二维码
