| 简介 |
A data processing apparatus has at least one memory and processing circuitry. A memory built-in self-test (MBIST) interface receives a MBIST request indicating that a test procedure is to be performed for testing at least one target memory location. Control circuitry detects the MBIST request and reserves for testing at least one reserved memory location including the target memory location. During the test procedure, the memory continues servicing memory transactions issued by the processing circuitry that target a memory location other than the reserved location reserved by the control circuitry. The processing circuitry is stalled if the processing circuitry attempts to access a reserved memory location. Testing consists of short bursts of transactions which occur infrequently. In this way, MBIST testing may continue while the processor is operation in the field with reduced performance impact.(16) Memory(17) Command cache unit(18) Data cache unit(19) TCM control unit(24) MBIST interface unit(30) External MBIST controller(4) Processor(5) Core(6) RegisterCOPYRIGHT KIPO 2016 |
客服热线：
手机版
二维码
