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FERMI-LEVEL UNPINNING STRUCTURES FOR SEMICONDUCTIVE DEVICES, PROCESSES OF FORMING SAME, AND SYSTEM 发明申请

2022-12-24 2030 1172K 0

专利信息

申请日期 2025-06-29 申请号 US14490581
公开(公告)号 US20150001644A1 公开(公告)日 2015-01-01
公开国别 US 申请人省市代码 全国
申请人 Intel Corporation
简介 An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.


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