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Semiconductor device and manufacturing method thereof 发明授权

2023-03-14 4400 422K 0

专利信息

申请日期 2025-09-14 申请号 JP2010159693
公开(公告)号 JP5557632B2 公开(公告)日 2014-07-23
公开国别 JP 申请人省市代码 全国
申请人 Renesas Electronics Corporation302062931
简介 A device isolation region is made of a silicon oxide film embedded in a trench, an upper portion thereof is protruded from a semiconductor substrate, and a sidewall insulating film made of silicon nitride or silicon oxynitride is formed on a sidewall of a portion of the device isolation region which is protruded from the semiconductor substrate. A gate insulating film of a MISFET is made of an Hf-containing insulating film containing hafnium, oxygen and an element for threshold reduction as main components, and a gate electrode that is a metal gate electrode extends on an active region, the sidewall insulating film and the device isolation region. The element for threshold reduction is a rare earth or Mg when the MISFET is an n-channel MISFET, and the element for threshold reduction is Al, Ti or Ta when the MISFET is a p-channel MISFET.


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