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High-K metal gate CMOS 发明授权

2023-03-05 4510 951K 0

专利信息

申请日期 2025-07-19 申请号 US13048170
公开(公告)号 US8507992B2 公开(公告)日 2013-08-13
公开国别 US 申请人省市代码 全国
申请人 Renee T Mo; Huiming Bu; Michael P Chudzik; William K Henson; Mukesh V Khare; Vijay Narayanan
简介 A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.


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