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HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED TRANSISTORS 发明申请

2023-06-20 1860 575K 0

专利信息

申请日期 2025-07-08 申请号 US13433659
公开(公告)号 US20120184093A1 公开(公告)日 2012-07-19
公开国别 US 申请人省市代码 全国
申请人 Michael P Chudzik; Naim Moumen; Vijay Narayanan; Dae Gyu Park; Vamsi K Paruchuri
简介 Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.


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