客服热线:18202992950

DOUBLE GATE FET AND FABRICATION PROCESS 发明申请

2023-07-28 3510 485K 0

专利信息

申请日期 2025-06-26 申请号 US12625967
公开(公告)号 US20100068858A1 公开(公告)日 2010-03-18
公开国别 US 申请人省市代码 全国
申请人 Petar B Atanakovic
简介 A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material, an upper gate insulating layer of crystalline rare earth insulating material, and an upper gate layer of crystalline rare earth conductive material. The upper gate layer and the upper gate electrically insulating layer are etched and a contact is deposited on the upper gate layer to define an upper gate structure. An impurity is implanted into the lower gate layer to define a lower gate area aligned with the upper gate structure. A source and drain are formed in the active layer and contacts are deposited on the source and drain, respectively.


您还没有登录,请登录后查看下载地址


反对 0举报 0 收藏 0 打赏 0评论 0
下载排行
网站首页  |  关于我们  |  联系方式  |  使用协议  |  版权隐私  |  网站地图  |  排名推广  |  广告服务  |  积分换礼  |  网站留言  |  RSS订阅  |  违规举报  |  京ICP备2021025988号-4