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FORMING METHOD BY WHICH DIELECTRIC STACK OF GATE IS CONTROLLED 发明申请

2023-10-15 1570 3628K 0

专利信息

申请日期 2026-03-24 申请号 JP2008002390
公开(公告)号 JP2008198995A 公开(公告)日 2008-08-28
公开国别 JP 申请人省市代码 全国
申请人 INTERUNIVERSITAIR MICRO ELEKTRONICA CENTRUM VZW; Taiwan Semiconductor Manufacturing Company Ltd
简介 PROBLEM TO BE SOLVED : To provide a controlled forming method for a gate dielectric stack. SOLUTION : A dielectric material layer is formed on a semiconductor substrate. Then, a rare earth oxide layer is deposited on the dielectric layer. After that, a metal gate electrode material is deposited on the rare earth oxide layer, and a rare earth silicate layer is formed by performing anealing. However, an annealing process is not performed before depositing the metal electrode material. COPYRIGHT : (C)2008, JPO&INPIT


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