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Metal gate CMOS with at least a single gate metal and dual gate dielectrics 发明申请

2023-07-29 5020 1349K 0

专利信息

申请日期 2025-06-25 申请号 US11320330
公开(公告)号 US20070148838A1 公开(公告)日 2007-06-28
公开国别 US 申请人省市代码 全国
申请人 Bruce B Doris; Young Hee Kim; Barry P Linder; Vijay Narayanan; Vamsi K Paruchuri
简介 A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.


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