LAMINATED CHIP VARISTOR

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PROBLEM TO BE SOLVED : To provide a laminated chip varistor that appropriately maintains ESD withstand, while reducing the capacitance. SOLUTION : A laminate 3 of the laminated chip varistor 1 has a varistor 7, and a pair of external layers 9 arranged so that the varistor 7 is sandwiched. The varistor 7 includes a varistor layer 11 manifesting the varistor characteristics itself, and a pair of internal electrodes 13 arranged so that the varistor layer 11 is sandwiched. The pair of internal electrodes 13 is electrically connected to the external electrodes 5. A region overlapping with the pair of internal electrodes 13 in the varistor layer 11 has a region, made of a first element body that has rare earth metal for manifesting the varistor characteristics itself, and a plurality of additives containing Co, as the auxiliary elements. The outer layer 9 has a region, made of a second element body that has ZnO as a main constituent, without containing Co, and containing only all additives except Co in the plurality of additives, as the auxiliary elements. COPYRIGHT : (C)2008, JPO&INPIT