Failure Detection and Mitigation in Logic Circuits

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PURPOSE : A method for failure detection and mitigation in logic circuits using a redundancy checker is provided to monitor the logic circuits about faults without problems of previous techniques such as a potential trouble of a system. CONSTITUTION : A single select parallel core is located in a test mode which neither affects a mission of logic circuits nor causes unintended actuations of output circuits. A redundancy checker controls a function of the select parallel core. An input or the inputs determined by internal states of the select parallel core are assigned. A response of the select parallel core is verified. The select parallel core is re-saved as a normal operation. [Reference numerals] (101) Core A; (102) Core B; (103) Redundancy checker; (AA) OUT